The present invention relates in general to integrated circuits, and in particular to a wide-range frequency synthesizer with programmable phase shift and high speed counters.
Frequency synthesizers are commonly found in circuit applications where periodic signals (e.g., clock signals) with accurate, user programmable frequencies are required. The use of phase-locked loops (PLLs) to implement frequency synthesizes are well known. A conventional PLL includes a phase detector that compares the phase of the loop frequency with an input (or reference) frequency. The output of the phase detector is typically filtered and applied to a voltage controlled oscillator (VCO). The frequency output of the VCO changes in the direction of the input reference frequency in response to the output of the phase detector. When the two signals reach the target phase relationship, the VCO frequency is said to be locked to that of the input frequency.
One type of circuit that uses a PLL is the programmable logic device (PLD). A PLD includes a large number of programmable logic cells interconnected by a programmable array of interconnects. The logic cells typically include clocked registers to implement sequential logic. The programmable resources within a PLD are configured by the user to perform a desired logic function. It is common to find a PLL on a PLD for the purpose of generating an internal clock signal to operate the various registers. The PLL is designed to generate an internal clock that meets the setup and hold time requirements of the PLD registers. The setup and hold time requirements for the PLD registers, however, vary depending on the configuration of the PLD. That is, depending on the configuration of the PLD, the location of the registers employed and their clocking requirements vary. Therefore, to ensure proper operation of the PLD regardless of the configuration, the PLL is usually designed for the worst case setup and hold time requirements. This results in less than optimum speed of operation for many configurations that could operate with tighter setup and hold times. Thus, this exemplary application highlights the need for a PLL that is capable of generating output signals across a wide range of frequencies and with programmable phase shift.